Market Definition and Business Model

Foundry is a business model in the semiconductor industry, referring to accepting the commission of other fabless semiconductor companies and specializing in the processing of finished wafers to manufacture integrated circuits, but not engaging in product design and back-end sales. Currently the key foundries are TSMC, Samsung Foundry, GlobalFoundries, United Microelectronics Corporation (UMC), SMIC, Tower Semiconductor, PSMC, VIS (Vanguard International Semiconductor), Hua Hong Semiconductor, and HLMC.

An Integrated Device Manufacturer (IDM) controls every process from planning to manufacturing and sales; a foundry only oversees production; and a fabless company only has the resources to design semiconductors. Most chips are fabricated outside of foundries. IDMs account for two-thirds of original chip sales, and 80% of chips outside the micro and logic segments. The most significant portion of chips manufactured by IDMs are memory chips, which are almost exclusively produced by a small group of IDMs. Discrete semiconductors are also nearly universally a product of IDMs. Analog integrated circuits, optoelectronics, and sensors and actuators are heavily, though not exclusively, provided by IDMs.

The importance of TSMC and Samsung foundry services to the global microelectronics ecosystem is difficult to overstate: the two companies’ foundries account for approximately 29% of global fabrication value and revenue. The global foundry market was USD 113.1 billion in 2023 and will reach USD 277.9 billion in 2030. In 2023, the top five foundries held over 83% share. According to QYResearch, the global top ten players held approximately 89.0% of revenue in 2023.

Recent Market Dynamics: TSMC’s Share Expansion and the 2nm Race

The concentration trajectory has accelerated since the 2023 base year. TrendForce data shows TSMC’s share of global foundry revenue rose from 62.8% in Q1 2024 to 70.4% in Q3 2025, with quarterly foundry revenue of USD 33.7 billion—nearly ten times its closest competitor . Samsung ranked second with 7.1% share, followed by SMIC at 5.2% and UMC at 4.2% . By Q3 2025, TSMC’s advanced-node revenue (7nm and below) accounted for 74% of wafer revenue, with 3nm at 23%, 5nm at 37%, and 7nm at 14%; HPC contributed 57% of total revenue . These figures illustrate a structural reality: the foundry market’s 89.0% top-ten concentration is not evenly distributed, and TSMC’s position at the leading edge is approaching monopoly.

The 2nm transition is reinforcing this hierarchy. TSMC’s 2nm process entered volume production in Q4 2025, with 15 confirmed customers—10 of them HPC—and Apple securing more than half of initial capacity. Monthly capacity is targeting 80,000 wafers in 2026 with a year-end sprint to 120,000 . Samsung’s 2nm trajectory, by contrast, has been slower: yield estimates ranged from approximately 20% in late 2025 to the 60% range by mid-2026, with reports of 80% unverified . Industry consensus places the mass-production threshold at roughly 70% yield, and Samsung has not yet announced a finalized large-scale contract with a major customer . The practical implication is that the 9.2% CAGR for the foundry market is not a uniform growth rate across suppliers; it is a weighted average in which TSMC captures the majority of leading-edge value while trailing-edge foundries compete on utilization and specialty processes.

The CoWoS Constraint: Foundry’s Packaging Bottleneck

The most consequential recent development in the foundry market is not a wafer node but a packaging technology. TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) capacity has become the binding constraint on AI accelerator shipments. Monthly CoWoS capacity is projected to increase from approximately 70,000 wafers in 2025 to 130,000–140,000 wafers by the end of 2026, yet the supply-demand gap is estimated to remain at approximately 20% . NVIDIA alone has reserved an estimated 800,000–850,000 wafers of TSMC’s 2026 CoWoS capacity—more than half the total—compressing availability for other customers .

TSMC has responded by expanding outsourcing of key CoWoS front-end steps to OSATs, and OSAT-added CoWoS capacity is estimated at 50,000–60,000 wafers per month, with ASE alone targeting 20,000–25,000 wafers per month of its CoWoP variant by year-end . This outsourcing does not diminish TSMC’s strategic position; it reinforces it. The foundry that controls both leading-edge wafer fabrication and the advanced packaging that integrates those wafers with HBM captures value that standalone OSATs cannot. The CoWoS constraint also explains why the foundry market’s growth rate exceeds the broader semiconductor manufacturing average: AI demand is pulling through foundry capacity and packaging capacity simultaneously, and the foundry tier captures the revenue for both.

Mature-Node Dynamics: Full Utilization and Strategic Divergence

The mature-node segment presents a different picture from the leading edge. Sigmaintell expects average capacity utilization at major fabs to reach roughly 91% in Q4 2026, driven by AI-supporting chip demand. UMC guides utilization above 91% for Q4 2026, more than 10 percentage points higher year-on-year, with 22/28nm utilization reaching approximately 93% . Mainland Chinese foundries such as SMIC, Hua Hong, and Nexchip have been running at full capacity since the beginning of the year . This utilization data complicates the narrative of a bifurcated market in which only leading-edge foundries prosper: mature-node demand for AI power management ICs, automotive electronics, and industrial control has tightened capacity at 8-inch and selected 12-inch nodes.

The strategic divergence is in pricing power. TSMC’s leading-edge capacity commands premium pricing because customers have no alternative for 3nm and 2nm production. Mature-node foundries, even at full utilization, face customer resistance to price increases in consumer electronics and handset segments, and Chinese foundries’ capacity additions constrain pricing discipline. The result is that the foundry market’s 9.2% CAGR is driven disproportionately by leading-edge price and mix, while mature-node growth is volume-driven and more cyclical.

Restraints

The principal restraint on foundry market growth is the capital intensity and geopolitical fragmentation of capacity expansion. A leading-edge fab costs upwards of USD 20 billion, and the return on that investment depends on utilization rates that fluctuate with demand cycles. Geographic diversification—new fabs in the United States, Europe, and Japan—increases costs because these locations lack the supplier ecosystems and labor pools of Taiwan and Korea. The U.S. government’s 10% stake in Intel, taken in August 2025, illustrates the political determination to preserve domestic foundry capability, but it also illustrates the gap between political objectives and commercial competitiveness: Intel’s foundry revenue was USD 223 million in Q3 2025, just 0.5% of the global total .

A second restraint is the CoWoS bottleneck described above. The 9.2% CAGR assumes that packaging capacity expands in line with wafer capacity; if it does not, the constraint will suppress foundry revenue even where wafer capacity is available. The supply-demand gap of approximately 20% in 2026 indicates that this restraint is active, not hypothetical.

Opportunity

The most significant opportunity is the geographic diversification of mature-node and specialty capacity. While leading-edge concentration dominates headlines, the majority of chip units are fabricated at mature nodes, and the geographic diversification of this capacity creates opportunities for regional foundries serving automotive, industrial, and consumer demand. Specialty processes for power, analog, and embedded memory are less capital-intensive than leading-edge logic and offer more stable returns. SMIC’s revenue growth from USD 1.5 billion in Q4 2022 to USD 2.5 billion in Q3 2025—a 70% increase despite U.S. export controls—demonstrates that domestic demand and government support can sustain mature-node foundry growth even under restricted access to advanced equipment .

A second opportunity lies in advanced packaging integration within foundry operations. TSMC’s CoWoS and SoIC expansion demonstrates that packaging is becoming a front-end capability rather than a back-end service. Foundries that integrate advanced packaging with wafer fabrication can offer turnkey solutions for AI and HPC customers, capturing value that would otherwise accrue to OSATs.

Analyst Observations

Two underappreciated dynamics merit attention. First, the 89.0% top-ten concentration understates the true concentration at the leading edge. TSMC alone holds 70% of global foundry revenue, and its share of leading-edge capacity (7nm and below) is higher still. The remaining 19 percentage points of top-ten concentration are distributed among Samsung, SMIC, UMC, GlobalFoundries, and Hua Hong—companies that compete in different segments and rarely go head-to-head with TSMC at the most advanced nodes. The strategic implication is that the foundry market is not a single competitive arena but two: a leading-edge oligopoly in which TSMC’s process leadership is unchallenged, and a mature-node market in which utilization and cost determine profitability. The 9.2% CAGR blends these two arenas, but the value accrues disproportionately to the first.

Second, the CoWoS constraint reveals that foundry competition is no longer solely about transistor density. A foundry that can fabricate 3nm wafers but cannot package them with HBM cannot serve AI customers. TSMC’s investment in CoWoS and SoIC is as strategically important as its investment in EUV lithography, and the outsourcing of CoWoS front-end steps to OSATs does not dilute this advantage—it extends the ecosystem’s capacity while keeping the critical integration step under TSMC’s control. For competitors, the lesson is that catching up at the leading edge requires not only process technology but also packaging technology and the customer relationships that co-optimize both. The 9.2% CAGR is achievable for the market as a whole, but the distribution of that growth will remain heavily skewed toward the foundry that controls both.

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